In general, systems used for information processing and communication include memory devices and logic devices for control, operation and interface functions. In conventional systems, the logic devices and the memory devices are typically on separate semiconductor chips. However, as the need for low cost systems increases, together with developments in semiconductor design and manufacturing technology, research has been conducted into a single semiconductor chip containing both logic devices and memory devices.
Technologies for integrating a logic semiconductor device and a small capacity SRAM onto a single chip are conventional, and such technologies may include application specific integrated circuit (ASIC) technologies. However, recently much research has been conducted into the technology of integrating a DRAM, particularly a common SDRAM having a large capacity, with logic devices on a single chip. Such technology has been referred to as merged-memory logic (MML) technology.
Although semiconductor devices have advanced using MML, it is impossible to connect every internal pad (for voltages or signals related to embedded memory) with an external pin, because of limitation in the number of external pins. Thus, the functional operation and AC parameters of an embedded memory have been tested using a direct access method. According to the direct access method, a tester can directly access the memory in a test mode. Here, the tester generates an address, test input and control signals according to a memory test algorithm and compare the test input with the data output. According to this method, a multiplexer is inserted into an input port of the memory and the input selected in a test mode is connected to IO pins, to thereby minimize design revisions. However, the direct access method has the disadvantage that the number of required test pins may be too large. Also, the additional delay from the output of the memory to the I/O pin may make test results unreliable. Thus, it may be difficult to accurately obtain AC parameters for the memory. Also, it may be difficult to test parameters at the real clock rate of 100 MHz because of memory tester limitations.
The functions and AC parameters of an embedded memory can also be tested using a built-in self test (BIST) method. In the BIST method, a BIST circuit is installed in an MML. The merit of this method is that the functions of the memory are measured at the real clock rate by using a logic tester. However, the BIST method shows the result of whether or not the memory has failure as only one bit. Thus, it may be difficult to detect the row and column addresses of the failed cells, so the application of a redundancy circuit is also complicated. Also, because a fail test is performed on all cells by using a read/write/read pattern composed of a single test parameter, it may be difficult to analyze which parameters have no margin.